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MP1531
Low Power, Triple Output Step-Up Plus Charge Pump for TFT Bias
The Future of Analog IC Technology
DESCRIPTION
The MP1531 is a triple output step-up converter with charge-pumps to make a complete DC/DC converter to power a TFT LCD panel from a 2.7V to 5.5V supply. The MP1531 includes a 250KHz fixed frequency step-up converter and a positive and negative linear regulator. The linear regulators are powered via charge-pumps driven by the step-up converter switch node. A single on/off control enables all 3 outputs. The outputs are internally sequenced at power-on for ease of use. An internal soft-start prevents overloading the input source at startup. Cycle-by-cycle current limit reduces component stress. The MP1531 is available in both a tiny 16-pin QFN package (3mm x 3mm) and a 16-pin TSSOP package.
FEATURES
* * * 2.7V to 5.5V Operating Input Range 500mA Switch Current Limit 3 Outputs in a Single Package * Step-Up Converter up to 22V * Positive 10mA Linear Regulator * Negative 10mA Linear Regulator 250m Internal Power MOSFET Switch 95% Efficiency 1A Shutdown Mode Fixed 250KHz Frequency Positive Regulator up to 38V Negative Regulator down to -20V Internal Power-On Sequencing Adjustable Soft-Start/Fault Timer Thermal Shutdown Cycle-By-Cycle Over Current Protection Under Voltage Lockout Ready Flag 16-Pin TSSOP and QFN (3mm x 3mm) Packages TFT LCD Displays Portable DVD Players Tablet PCs Car Navigation Displays
EVALUATION BOARD REFERENCE
Board Number EV1531DQ-002A Dimensions 2.3"X x 2.3"Y x 0.5"Z
* * * * * * * * * * * * * * * * *
APPLICATIONS
"MPS" and "The Future of Analog IC Technology" are Registered Trademarks of Monolithic Power Systems, Inc.
TYPICAL APPLICATION
VIN 2.7V-4.2V
Efficiency vs Load Current
100 90 VIN = 4.2V VIN = 3.3V
EFFICIENCY (%)
OFF ON TO SW
EN CT RDY IN SW COMP FB1
VMAIN 5V
80 70 60 50 40 30 20 0
IN2
MP1531
VGL -4V
IN3 GL FB2 REF GND GH FB3 PGND
VGH 12V
VMAIN = 5V 100 200 300 400 500 600 LOAD CURRENT (mA)
MP1531 Rev. 1.2 5/22/2006
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MP1531 - LOW POWER, TRIPLE OUTPUT STEP-UP PLUS CHARGE PUMP FOR TFT BIAS
PACKAGE REFERENCE
PIN 1 ID PGND 16 SW CT RDY FB1 1 2 3 4 5 COMP 6 IN 7 GND 8 REF
TOP VIEW
IN3 15 GH 14 IN2 13 12 11 10 9 GL EN FB3 FB2
TOP VIEW
RDY FB1 COMP IN GND REF FB2 FB3 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 CT SW PGND IN3 GH IN2 GL EN
EXPOSED PAD CONNECT TO PIN 13
Part Number* MP1531DQ *
Package QFN16 (3mmx3mm)
Temperature -40C to +85C
Part Number** MP1531DM
Package TSSOP16
Temperature -40C to +85C
For Tape & Reel, add suffix -Z (eg. MP1531DQ-Z) For RoHS compliant packaging, add suffix -LF (eg. MP1531DQ-LF-Z)
** For Tape & Reel, add suffix -Z (eg. MP1531DM-Z)
For RoHS compliant packaging, add suffix -LF (eg. MP1531DM-LF-Z)
ABSOLUTE MAXIMUM RATINGS (1)
IN Supply Voltage ..........................-0.3V to +6V SW Voltage ..................................-0.3V to +25V IN2, GL Voltage ...........................+0.3V to -25V IN3, GH Voltage...........................-0.3V to +40V IN2 to IN3 Voltage .......................-0.3V to +60V All Other Pins .................................-0.3V to +6V Junction Temperature ...............................125C Lead Temperature ....................................260C Storage Temperature ............. -65C to +150C
Recommended Operating Conditions (2)
Input Voltage .................................. 2.7V to 5.5V Main Output Voltage...........................VIN to 22V IN2, GL Voltage ................................ 0V to -20V IN3, GH Voltage ................................. 0V to 38V Operating Temperature .............-40C to +85C
Thermal Resistance (3)
QFN16 .................................... 60 ..... 120.. C/W TSSOP16 ............................... 90 ...... 30... C/W
Notes: 1) Exceeding these ratings may damage the device. 2) The device is not guaranteed to function outside of its operating conditions. 3) Measured on approximately 1" square of 1 oz copper.
JA
JC
ELECTRICAL CHARACTERISTICS (4)
VIN = 5.0V, TA = +25C, unless otherwise noted.
Parameter Input Voltage Range IN Undervoltage Lockout Threshold IN Undervoltage Lockout Hysteresis IN Shutdown Current IN Quiescent Current EN Input High Voltage EN Input Low Voltage EN Hysteresis EN Input Bias Current
MP1531 Rev. 1.2 5/22/2006
Symbol Condition VIN VUVLO IN Rising VEN < 0.3V VEN > 2V, VFB1 = 1.4V EN Rising
Min 2.7 2.25
Typ
Max 5.5 2.65 1 1.5 0.3
100 0.5 0.8 1.6 100
VEN-HIGH
1
Units V V mV A mA V V mV A 2
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MP1531 - LOW POWER, TRIPLE OUTPUT STEP-UP PLUS CHARGE PUMP FOR TFT BIAS
ELECTRICAL CHARACTERISTICS (4) (continued)
VIN = 5.0V, TA = +25C, unless otherwise noted.
Parameter Oscillator Switching Frequency Maximum Duty Cycle Soft-Start Period Turn-Off Delay Error Amplifier Error Amplifier Voltage Gain Error Amplifier Transconductance COMP Maximum Output Current FB1, FB3 Regulation Voltage FB2 Regulation Voltage FB1, FB3 Input Bias Current FB2 Input Bias Current Reference (REF) REF Regulation Voltage REF Load Regulation Output Switch (SW) SW On Resistance SW Current Limit SW Leakage Current GL Dropout Voltage (5) GH Dropout Voltage (5) GL Leakage Current GH Leakage Current Thermal Shutdown ILIM VSW = 22V VGL = -10V, IGL = 10mA VGH = 20V, IGH = 10mA VIN2 = -15V, VGL = GND VIN3 = 25V, VGH = GND Symbol Condition fSW DM C4 = 10nF AvEA GmEA 1.22 -25 VFB1 = VFB3 = 1.25V VFB2 = 0V IREF = 50A 0A < IREF < 200A VIN = 5V VIN = 3V 0.5 1.22 Min 200 85 Typ 250 90 6 3 400 1000 100 1.25 0 100 100 1.25 1 250 400 0.65 0.5 Max 300 Units KHz % ms s V/V A/V A V mV nA nA V % m m A A V V A A C
1.28 +25
1.28 1.2
1 0.15 0.5 1 1
160
Notes: 4) Typical values are guaranteed by design, not production tested. 5) Dropout voltage is the input to output differential at which the circuit ceases to regulate against further reduction in input voltage.
TYPICAL PERFORMANCE CHARACTERISTICS
Circuit of Figure 3, unless otherwise noted. Load Transient
Power-Up Sequencing
VIN = 3.3V, VMAIN = 5V, IMAIN = 100mA, VGH = 15V, IGH = 5mA, VGL = -10V, IGL = 5mA
Efficiency vs Load Current Delivered by Step-Up Converter
100 90 VIN = 4.2V VIN = 3.3V
VMAIN 50mV/div
VIN = 3.3V, VMAIN = 5V, 5mA-50mA Step, VGH = 15V, IGH = 5mA, VGL = -10V, IGL = 5mA
EFFICIENCY (%)
80 70 60 50 40 30 20 0
VEN 5V/div VMAIN 5V/div VGH 10V/div VGL 10V/div
IMAIN 50mA/div
VMAIN = 5V 100 200 300 400 500 600 LOAD CURRENT (mA) 10ms/div
MP1531 Rev. 1.2 5/22/2006
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MP1531 - LOW POWER, TRIPLE OUTPUT STEP-UP PLUS CHARGE PUMP FOR TFT BIAS
PIN FUNCTIONS
QFN16 TSSOP16 Pin # Pin # Name Description 1 15 SW Step-Up Converter Power Switch Node. Connect an inductor between the input source and SW, and connect a rectifier from SW to the main output to complete the step-up converter. SW is the drain of the internal 250m N-Channel MOSFET switch. 2 16 CT Timing Capacitor for Soft-Start and Power-On Sequencing. A capacitor from CT to GND controls the soft-start and sequencing turn-on delay periods. See Power-On Sequencing and Start-Up Timing Diagram. 3 1 RDY Regulators Not Ready. This pin is an open drain output, and an external 100k pull-up resistor is required for proper operation. During startup RDY will be high impedance. Once the turn-on sequence is complete, this pin will be pulled low if all FB voltages exceed 80% of their specified thresholds. After all regulators are turned-on, a fault in any regulator that causes the respective FB voltage to fall below 80% of its threshold will cause RDY to go high after approximately 15s. If the fault persists for more than approximately 6ms (for C4 = 10nF), the entire chip will shut down. See Fault Sensing and Timer. FB1 Step-Up Converter Feedback Input. FB1 is the inverting input of the internal error amplifier. Connect a resistive voltage divider from the output of the step-up converter to FB1 to set the step-up converter output voltage. COMP Step-Up Converter Compensation Node. COMP is the output of the error amplifier. Connect a series RC network to compensate the regulation control loop of the step-up converter. IN Internal Power Input. IN supplies the power to the MP1531. Bypass IN to PGND with a 10F or greater capacitor. GND Signal Ground. REF Reference Output. REF is the 1.25V reference voltage output. Bypass REF to GND with a 0.1F or greater capacitor. Connect REF to the low-side resistor of the negative linear regulator feedback string. FB2 Negative Linear Regulator Feedback Input. Connect the FB2 feedback resistor string between GL and REF to set the negative linear regulator output voltage. FB2 regulation threshold is GND. FB3 Positive Linear Regulator Feedback Input. Connect the FB3 feedback resistor string between GH and GND to set the positive linear regulator output voltage. FB3 regulation threshold is 1.25V. EN On/Off Control Input. Drive EN high to turn on the MP1531, drive EN low to turn it off. For automatic startup, connect EN to IN. Once the MP1531 is turned on, it sequences the outputs on (See Power-On Sequencing). When turned off, all outputs are immediately disabled. GL Negative Linear Regulator Output. GL is the output of the negative linear regulator. GL can supply up to 10mA to the load. Bypass GL to GND with a 1F or greater, low-ESR, ceramic capacitor. IN2 Negative Linear Regulator Input. IN2 is the input of the negative linear regulator. Drive IN2 with an inverting charge pump powered from SW. IN2 can go as low as -20V. For QFN package IN2 connects to exposed pad. GH Positive Linear Regulator Output. GH is the output of the positive linear regulator. GH can supply as much as 10mA to the load. Bypass GH to GND with a 1F or greater, low-ESR, ceramic capacitor. IN3 Positive Linear Regulator Input. IN3 is the input to the positive linear regulator. Drive IN3 with a doubling, tripling, or quadrupling charge pump from SW. IN3 voltage can go as high as 38V. PGND Power Ground. PGND is the source of the internal 250m N-Channel MOSFET switch. Connect PGND to GND as close to the MP1531 as possible.
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MP1531 Rev. 1.2 5/22/2006
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MP1531 - LOW POWER, TRIPLE OUTPUT STEP-UP PLUS CHARGE PUMP FOR TFT BIAS
OPERATION
The MP1531 is a step-up converter with two integrated linear regulators to power TFT LCD panels. Typically the linear regulators are powered from diode charge-pumps driven from the switch node (SW). The user can set the positive charge-pump to be a doubler, tripler, or quadrupler to achieve the required linear regulator input voltage for the selected output voltage. Typically the negative charge-pump is configured as a 1x or 2x inverter.
IN
REFERENCE VREF + GM FB1 COMP -PULSE-WIDTH MODULATOR
REF
SW
OSCILLATOR 0.8VREF + 0.8VREF + PGND
-0.2VREF +
SOFT-START FAULT TIMER & SEQUENCING
--EN CT FB2 + -IN2 GH GL RDY -VREF
+
FB3 IN3
GND
Figure 1--Functional Block Diagram
MP1531 Rev. 1.2 5/22/2006
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MP1531 - LOW POWER, TRIPLE OUTPUT STEP-UP PLUS CHARGE PUMP FOR TFT BIAS Step-Up Converter The 250KHz fixed-frequency step-up converter employs a current-mode control architecture that maximizes loop bandwidth to provide fasttransient responses needed for TFT LCD drivers. High switching frequency allows for smaller inductors and capacitors minimizing board space and thickness. Linear Regulators The positive linear regulator (GH) uses a P-Channel pass element to drop the input voltage down to the regulated output voltage. The feedback of the positive linear regulator is a conventional error amplifier with the regulation threshold at 1.25V. The negative linear regulator (GL) uses a N-Channel pass element to raise the negative input voltage up to the regulated output voltage. The feedback threshold for the negative linear regulator is ground. The resistor string goes from REF (1.25V) to FB2 and from FB2 to GL to set the negative output voltage, VGL. The difference between the voltage at IN3 and the voltage at IN2 is limited to 60V abs. max. Fault Sensing and Timer Each of the 3 outputs has an internal comparator that monitors its respective output voltage by measuring the voltage at its respective FB input. When any FB input indicates that the output voltage is below approximately 80% of the correct regulation voltage, the fault timer enables and the RDY pin goes high impedance. The fault timer uses the same CT capacitor as the soft-start sequencer. If any fault persists to the end of the fault timer (One CT cycle is 6ms for a 10nF capacitor), all outputs are disabled. Once the outputs are shut down due to the fault timer, the MP1531 must be re-enabled by either cycling EN or by cycling the input power. When reenabled, the MP1531 cycles through the normal power-on sequence. If the fault persists for less than the fault timer period, RDY will be pulled low and the part will function as though no fault has occurred. Power-On Sequencing and Soft-Start The MP1531 automatically sequences its outputs at startup. When EN goes from low to high, or if EN is held high and the input voltage VIN rises above the under-voltage lockout threshold, the outputs turn on in the following sequence: 1. Step-up converter 2. Negative linear regulator (GL) 3. Positive linear regulator (GH) Each output turns on with a soft-start voltage ramp. The soft-start ramp period is set by the timing capacitor connected between CT and GND. A 10nF capacitor at CT sets the soft-start ramp period to 6ms. The timing diagram is shown in Figure 2. After the MP1531 is enabled, the power-on reset spans three periods of the CT ramp. First the step-up converter is powered up with reference to the CT ramp and allowed one period of the CT ramp to settle. Next the negative linear regulator (GL) is soft-started by ramping REF, which coincides with the CT ramp, and also allowed one CT ramp period to settle. The positive linear regulator (GH) is then soft-started and allowed to settle in one period of CT ramp. Nine periods of the CT ramp have occurred since the chip enabled. If all outputs are in regulation (>80%), the CT will stop ramping and be held at ground. The RDY pin will be pulled down to an active low. If any FB voltage remains below regulation (<80%) after the nine CT periods, RDY will remain high and CT will begin its fault timer pulse.
MP1531 Rev. 1.2 5/22/2006
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MP1531 - LOW POWER, TRIPLE OUTPUT STEP-UP PLUS CHARGE PUMP FOR TFT BIAS
VGH
OUTPUT VOLTAGES
VMAIN
VIN 0V
VGL VIN IN 0V VEN-HIGH EN 0V POWER ON RESET 1.25V CT 0V VIN RDY 0V TIME START 1 START 2 START 3
Figure 2--Start-Up Timing Diagram
APPLICATION INFORMATION
Setting the Output Voltages Set the output voltage on each output by selecting the resistive voltage divider ratio. The voltage divider drops the output voltage to the feedback threshold voltage. Use 10k to 50k for the low-side resistor of the voltage divider. For the step-up converter, determine the high-side resistor R1 by the equation:
R1 = VMAIN - VFB1 VFB1 R2
For the positive charge-pump, determine the high-side resistor R9 by the equation:
R9 = VGH - VFB3 VFB3 R8
For the negative charge-pump, determine the high-side resistor R7 by the equation:
R7 = - VGL VREF R5
Where VMAIN is the output voltage of the step-up converter.
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MP1531 - LOW POWER, TRIPLE OUTPUT STEP-UP PLUS CHARGE PUMP FOR TFT BIAS Selecting the Inductor The inductor is required to force the higher output voltage while being driven by the input voltage. A larger value inductor results in less ripple current that results in lower peak inductor current. However, the larger value inductor has a larger physical size, higher series resistance, lower saturation current for a given package size. Choose an inductor that does not saturate at heavy load transients and start-up conditions. A good rule for determining the inductance is to allow the peak-to-peak ripple current to be approximately 30-50% of the maximum input current. Make sure that the peak inductor current is below the device current limit to prevent loss of regulation. Calculate the required inductance value by the equation:
VIN (VMAIN - VIN ) VMAIN x f SW x I
L1 =
Where VIN is the input voltage, fSW is the switching frequency, and I is the peak-to-peak inductor ripple current. Selecting the Input Capacitor An input capacitor is required to supply the AC ripple current to the inductor, while limiting noise at the input source. A low ESR capacitor is required to keep the noise at the IC to a minimum. Since it absorbs the input switching current it requires an adequate ripple current rating. Use a capacitor with RMS current rating greater than the inductor ripple current (see Selecting The Inductor to determine the inductor ripple current). The input capacitor in Figure 3 is necessary in most lab setups, but can be reduced in typical application circuits if the source impedance is lower.
VIN 2.7V to 4.2V
C4 10nF CT EN RDY COMP C3 10nF IN2 D7 BAS40-04-7 D6 BAS40-04-7 D5 BAS40-04-7 GL FB2 C9 56pF REF GND FB3 PGND C7 56pF IN SW FB1 D1 B0530W
OFF ON RDY SW
VMAIN 5V
D2 BAS40-04-7
MP1531
IN3 D4 BAS40-04-7 GH D3 BAS40-04-7
VGL -10V
VGH 15V
Figure 3--Triple Output Boost Application Circuit
MP1531 Rev. 1.2 5/22/2006
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MP1531 - LOW POWER, TRIPLE OUTPUT STEP-UP PLUS CHARGE PUMP FOR TFT BIAS To insure stable operation place the input capacitor as close to the IC as possible. Alternately a smaller high quality 0.1F ceramic capacitor may be placed closer to the IC if the larger capacitor is placed further away. Selecting the Rectifier Diodes Schottky diodes are recommended for most applications because of their fast recovery time and low forward voltage. Use Schottky diodes with a current rating equal to or greater than 4 times the average output current, and a voltage rating at least 1.5 times VGH for the positive charge-pump and VGL for the negative chargepump. 100mA Schottky diodes such as Central Semiconductor CMPSH-3 are recommended for low current charge-pump circuits. Selecting the Output Capacitor of the StepUp Converter The output capacitor is required to maintain the DC output voltage. Low ESR capacitors are preferred to keep the output voltage ripple to a minimum. The characteristics of the output capacitor also affect the stability of the regulation control system. A 10-22F ceramic capacitor works well in most applications. In the case of ceramic capacitors, the impedance of the capacitor at the switching frequency is dominated by the capacitance, and so the output voltage ripple is mostly independent of the ESR. The output voltage ripple is estimated to be:
VRIPPLE ( VMAIN - VIN ) x ILOAD VMAIN x C2 x f SW
dropout margin for the linear regulator. The positive charge-pump can also be configured based on VIN for better efficiency. Then the equation will be:
NPOS
(VGH + VDROPOUT
- VIN )
VMAIN - 2 x VD
The number of negative charge-pump stages NNEG is approximately given by:
NNEG - VGL + VDROPOUT VMAIN - 2 x VD
Use VDROPOUT = 0.5V for positive charge-pump and VDROPOUT = 0.15V for negative charge-pump. Selecting the Flying Capacitor in ChargePump Stages Increasing the flying capacitor CX values increases the output current capability. A 0.33F ceramic capacitor works well in most low current applications. The flying capacitor's voltage rating must exceed the following:
VCX > N x VMAIN
Where N is the stage number in which the flying capacitor appears. Step-Up Converter Compensation The MP1531 uses current-mode control which unlike voltage mode has only a single pole roll off due to the output filter. The DC gain (AVDC) is equated from the product of current control to output gain (AVCSCONTROL), error amplifier gain (AVEA), and the feedback divider.
Av DC = A CSCONTROL x Av EA x A FB1 A CSCONTROL = 4 x A FB1 = Av DC = VFB1 VMAIN VIN ILOAD
Where VRIPPLE is the output ripple voltage, ILOAD is the load current, and C2 is the capacitance of the output capacitor of the step-up converter. Selecting the Number of Charge-Pump Stages For highest efficiency, always choose the lowest number of charge-pump stages that meets the output requirement. The number of positive charge-pump stages NPOS is approximately given by:
NPOS
1600 x VIN x VFB1 ILOAD x VMAIN
The output filter pole is given in hertz by:
fFILTERPOLE = ILOAD x VMAIN x C2
(VGH + VDROPOUT
VMAIN
- VMAIN ) - 2 x VD
Where VD is the forward voltage drop of the charge-pump diode, and VDROPOUT is the
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MP1531 - LOW POWER, TRIPLE OUTPUT STEP-UP PLUS CHARGE PUMP FOR TFT BIAS The output filter zero is given in hertz by:
fFILTERZERO = 1 2 x x R ESR x C2
For the positive linear regulator:
fPOSPOLE1 = 1 2 x x (R10 + R9 || R8 ) x C7 1 2 x x (R10 + R9 ) x C7
Where RESR is the equivalent series resistance of the output capacitor. With all boost regulators the right half plane zero (RHPZ) is given in hertz by:
fRHPZ V VMAIN = IN x V 2 x x ILOAD x L1 MAIN
2
fPOSZERO1 =
For the negative linear regulator:
fNEGPOLE1 = 1 2 x x (R6 + R7 || R5 ) x C9
1 2 x x (R6 + R7 ) x C9
Error Amplifier Compensation To stabilize the feedback loop dynamics the error amplifier compensation is as follows:
fPOLE1 1 2 x x 10 6 x C3
fNEGZERO1 =
fPOSPOLE1 and fNEGPOLE1 are necessary to cancel out the zero created by the equivalent series resistance (RLDOESR) of the output capacitor.
fLDOZERO = 1 2 x x R LDOESR x C LDO
f ZERO1
1 = 2 x R3 x C3
Where R3 and C3 are part of the compensation network in Figure 3. A good start is 5.6k and 10nF. This combination gives about 70 of phase margin and bandwidth of about 35KHz for most load conditions. Increasing R3 and/or reducing C3 increases the loop bandwidth and improves the load transient. Linear Regulator Compensation The positive or negative regulated voltages of two linear regulators are controlled by a transconductance amplifier and a P-channel or N-Channel pass transistor respectively. The DC gain of either LDO is approximately 100dB with a slight dependency on load current. The output capacitor (CLDO) and resistance load (RLOAD) make-up the dominant pole.
fLDOPOLE1 = 1 2 x x R LOAD x C LDO
For component values shown in Figure 3 a 10 and 56pF RC network gives about 45 of phase margin and a bandwidth of about 35KHz on both regulators. Layout Considerations Careful PC board layout is important to minimize ground bounce and noise. First, place the main boost converter inductor, output diode and output capacitor as close to the SW and PGND pins as possible with wide traces. Then place ceramic bypass capacitors near IN, IN2 and IN3 pins to the PGND pin. Keep the charge-pump circuitry close to the IC with wide traces. Locate all FB resistive dividers as close to their respective FB pins as possible. Separate GND and PGND areas and connect them at one point as close to the IC as possible. Avoid having sensitive traces near the SW node and high current lines. Refer to the MP1531 demo board for an example of proper board layout.
The pass transistor's internal pole is about 10Hz to 30Hz. To compensate for the two pole system and add more phase and gain margin, a lead-lag resistor capacitor network is necessary.
MP1531 Rev. 1.2 5/22/2006
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MP1531 - LOW POWER, TRIPLE OUTPUT STEP-UP PLUS CHARGE PUMP FOR TFT BIAS
PACKAGE INFORMATION
QFN16 (3mm x 3mm)
MP1531 Rev. 1.2 5/22/2006
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MP1531 - LOW POWER, TRIPLE OUTPUT STEP-UP PLUS CHARGE PUMP FOR TFT BIAS
TSSOP16
NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications.
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